Not Applicable.
The present embodiments relate to electronic circuit devices and are more particularly directed to dynamic logic circuits using transistors having differing threshold voltages and delayed low threshold voltage leakage protection.
Electronic circuits have become prevalent in numerous applications, including uses for devices in personal, business, and other environments. Demands of the marketplace affect many aspects of circuit design, including factors such as device power consumption and speed. Various electronic circuits now implement what is known in the art as dynamic, or domino, logic. Dynamic logic circuitry operates in two phases, a precharge phase during which one or more precharge nodes are precharged to a first voltage, and an evaluate phase during which the data is read based on the voltage at each precharge node, where the precharge voltage therefore may be read as a first logic state if undisturbed or where that precharge voltage may be first discharged and then read as a second logic that is complimentary to the first logic state. Further, dynamic logic often passes signals through two or more stages, so that an evaluation by a first stage that discharges the first stage precharge node results in an output to the input of a second stage, and where that signal also thereby triggers a discharge of a precharge node in the second stage. In this manner, a number of stages may be triggered as the evaluate phases of the stages overlap and the output of each stage propagates through to the next successive stage.
The art has recognized that current may leak from the dynamic logic precharge node during its evaluate phase in the instance when the discharge path to that precharge node is not enabled during that evaluate phase. Indeed, it is known in the art that the discharge path of the dynamic logic stage may include one or more so-called low threshold voltage (xe2x80x9cLVTxe2x80x9d) transistors, where such transistors are sometimes used in a discharge path in order to increase the speed of that path when the path is enabled. In such a case, each LVT transistor has a relatively lower threshold transistor as compared to other transistors in the same circuit, and such other transistors are therefore referred to as high threshold voltage (xe2x80x9cHVTxe2x80x9d) transistors. In one previous approach, at least one HVT transistor is also included in the discharge path. Indeed, for numerous additional details relating to such an approach and related aspects, the reader is invited to review U.S. Pat. No. 5,831,451, entitled xe2x80x9cDynamic Logic Circuits Using Transistors Having Differing Threshold Voltages,xe2x80x9d issued Nov. 3, 1998, having the same inventor and assignee of the subject application, and U.S. Pat. No. 5,821,778, entitled xe2x80x9cUsing cascode transistors having low threshold voltages,xe2x80x9d issued Oct. 13, 1998, having the same inventor and assignee of the subject application, where both of these two patents are hereby incorporated herein by reference. In any event, the use of an LVT transistor (or more than one such transistor) correspondingly provides increased leakage when it is not enabled and, as such, when implemented in the discharge path of a dynamic logic stage, that transistor increases leakage when that discharge path is not enabled. Increased leakage is undesirable because it increases device power consumption and, indeed, if severe, may jeopardize the proper operation of the circuit.
By way of further background, in dual rail dynamic logic circuits an approach has been implemented in an effort to alleviate the above-described leakage that occurs from the precharge node during the evaluate phase. Specifically, dual rail dynamic logic circuits include two precharge nodes, where during the evaluate phase one or the other of the precharge nodes is, by definition of the dual-rail system, assured to discharge, while at the same time therefore the other of the two precharge nodes remains charged. Thus, the charged precharge node can leak, particularly if there are one or more LVT transistors in a discharge path connected to the charged precharge node. Also in such a circuit, however, often a cross-coupled pair of LVT p-channel transistors is connected such that the source/drain path of each such transistor is connected to a respective precharge node while the gate of each respective transistor is connected to the opposite respective precharge node. As a result, when one precharge node is discharged low, that same node provides an enabling voltage to the opposing cross-coupled p-channel transistor, and that transistor, when enabled, conducts a source voltage to the opposing precharge node, thereby maintaining it at a sufficient level despite any leakage through its respective discharge path. Moreover, note in this case that the cross-coupled transistors are LVT transistors; as such, the LVT transistor provides a less-resistive connection between VDD and the precharge node as compared to an HVT transistor. This is desirable, particularly at low operating voltages, when the relative drive currents of HVT transistors may diminish considerably as compared to their LVT counterparts. Also, the use of an LVT p-channel transistor in this manner is desirable because using an HVT transistor to provide such a coupling may prove insufficient to hold the precharge node at a sufficient voltage against the leakage of one or more LVT transistors in the discharge path. Still further, without sufficiently holding the precharge voltage high under these circumstances, insufficient noise margin may result and dynamic nodes may switch when they are not supposed to, due to noise or leakage currents, or both.
By way of still further background, in single rail dynamic logic circuits, it is known in the art to include an HVT p-channel transistor as a feedback, or sometimes referred to as a xe2x80x9ckeeperxe2x80x9d transistor, connected such that the transistor gate is connected to the circuit output, the transistor source is connected to a voltage source, and the transistor drain is connected to the precharge node. In this manner, when the dynamic logic circuit is in its evaluate phase but its discharge path is not enabled, then the high precharge voltage is inverted and applied to the gate of the feedback transistor. In response, that transistor conducts and thereby couples the source voltage to the precharge node. In theory, therefore, this coupling of voltage offsets any leakage that may occur through the discharge path of the circuit. Moreover, the single feedback p-channel transistor cannot simply be made to be an LVT transistor because then, in instances when the discharge path is fully enabled and includes an HVT transistor, that HVT transistor included in the discharge path may provide a limit that keeps the discharge path from satisfactorily pulling down the precharge node, since that precharge node would be connected to a source voltage through a less-resistive LVT p-channel transistor. In other words, the HVT discharge path transistor may not provide sufficient drive current to overcome the LVT feedback p-channel transistor.
While the preceding approaches implemented with respect to dynamic logic circuits have proven satisfactory in many applications, the leakage in the discharge path of the circuit may be unacceptable, particularly when the leakage in that path is increased due to the use of one or more LVT n-channel transistors. Further, while an HVT p-channel keeper transistor may provide some current to compensate for the leakage of an LVT n-channel transistor in a single rail dynamic logic circuit, it has been recognized in connection with the preferred embodiments that such an approach alone may not be satisfactory for various reasons. Specifically, in order for the HVT p-channel keeper transistor to serve its purpose in this regard, the current it provides when enabled (i.e., the xe2x80x9con-currentxe2x80x9d of the p-channel transistor) must be sufficiently larger than the leakage current of the LVT n-channel transistor (i.e., the xe2x80x9coff-currentxe2x80x9d of the n-channel transistor). However, this goal is becoming increasingly more difficult because there are various factors that are tending to decrease the ratio of the on-current of the HVT p-channel transistor relative to the off-current of the LVT n-channel transistor. For example, as the system source voltage, VDD, decreases in circuit design as is the current trend, the above-described current ratio decreases. As another factor, transistor threshold voltage is a function of temperature, that is, high temperatures decrease threshold voltage, and this too decreases the subject current ratio. As still another factor, there is a trend to build many low threshold voltage transistors in a manner to provide more drive current, once more decreasing the above-discussed ratio. Finally, n-channel transistors are stronger in current provision than p-channel transistors, still again decreasing the above-discussed ratio. With these factors, note therefore that the HVT p-channel transistor attempts to source sufficient current to compensate for the leakage of the LVT n-channel transistor, but in that attempt an increasingly larger amount of voltage is dropped across the HVT p-channel transistor, particularly in a relative sense as its strength is reduced relative to that of the n-channel transistor. The increase in voltage drop may be detrimental for various reasons, including calling into question the reliability of data validity of the dynamic logic circuit. However, because the feedback transistor is an HVT transistor, it is likely unable to provide sufficient current to offset the larger amount of current that may be lost through leakage of any LVT transistor in the circuit discharge path.
Given the preceding, the preferred embodiments seek to improve upon the limitations and drawbacks of the prior art, as discussed in detail below.
In the preferred embodiment, there is a dynamic logic circuit. The dynamic logic circuit comprises a precharge node to be precharged to a precharge voltage during a precharge phase and a conditional discharge path connected to the precharge node. The conditional discharge path is operable, during an evaluate phase, to conditionally couple the precharge node to a voltage different than the precharge voltage. The dynamic logic circuit also comprises an output for providing a signal in response to a state at the precharge node. Lastly, the dynamic logic circuit comprises voltage maintaining circuitry, coupled to the output, for coupling the precharge voltage to the precharge node during a portion of an instance of the evaluate phase when the conditional discharge path is not enabled during the instance of the evaluate phase.
Other aspects are also disclosed and claimed.